1. Field of the Invention
Generally, the present invention relates to the formation of microstructures, such as advanced integrated circuits, and, more particularly, to the formation of conductive structures, such as copper-based interconnect lines, and techniques to reduce their degradation during stress conditions.
2. Description of the Related Art
In the fabrication of modern microstructures, such as integrated circuits, there is a continuous drive to steadily reduce the feature sizes of microstructure elements, thereby enhancing the functionality of these structures. For instance, in modern integrated circuits, minimum feature sizes, such as the channel length of field effect transistors, have reached the deep sub-micron range, thereby increasing performance of these circuits in terms of speed and/or power consumption. As the size of individual circuit elements is reduced with every new circuit generation, thereby improving, for example, the switching speed of the transistor elements, the available floor space for interconnect lines electrically connecting the individual circuit elements is also decreased. Consequently, the dimensions of these interconnect lines also have to be reduced to compensate for a reduced amount of available floor space and an increased number of circuit elements provided per unit die area, as typically the number of interconnections required increases more rapidly than the number of circuit elements. Thus, a plurality of stacked “wiring” layers, also referred to as metallization layers, are usually provided, wherein individual metal lines of one metallization layer are connected to individual metal lines of an overlying or underlying metallization layer by so-called vias. Despite the provision of a plurality of metallization layers, reduced dimensions of the interconnect lines are necessary to comply with the enormous complexity of, for instance, modern CPUs, memory chips, ASICs (application specific ICs) and the like. The reduced cross-sectional area of the interconnect structures, possibly in combination with an increase of the static power consumption of extremely scaled transistor elements, may result in considerable current densities in the metal lines.
Advanced integrated circuits, including transistor elements having a critical dimension of 0.13 μm and even less, may, therefore, require significantly increased current densities of up to several kA per cm2 in the individual interconnect structures, despite the provision of a relatively large number of metallization layers, owing to the significant number of circuit elements per unit area. Operating the interconnect structures at elevated current densities, however, may entail a plurality of problems related to stress-induced line degradation, which may finally lead to a premature failure of the integrated circuit. One prominent phenomenon in this respect is the current-induced material transportation in metal lines and vias, also referred to as “electromigration,” which may lead to the formation of voids within and hillocks next to the metal interconnect, thereby resulting in reduced performance and reliability or complete failure of the device. For instance, aluminum lines embedded into silicon dioxide and/or silicon nitride are frequently used as metal for metallization layers, wherein, as explained above, advanced integrated circuits having critical dimensions of 0.18 μm or less, may require significantly reduced cross-sectional areas of the metal lines and, thus, increased current densities, which may render aluminum less attractive for the formation of metallization layers.
Consequently, aluminum is being replaced by copper, a material with significantly lower resistivity and improved resistance to electromigration even at considerably higher current densities compared to aluminum. The introduction of copper into the fabrication of microstructures and integrated circuits comes with a plurality of severe problems residing in copper's characteristic to readily diffuse in silicon dioxide and a plurality of low-k dielectric materials. To provide the necessary adhesion and to avoid the undesired diffusion of copper atoms into sensitive device regions, it is, therefore, usually necessary to provide a barrier layer between the copper and the dielectric material in which the copper-based interconnect structures are embedded. Although silicon nitride is a dielectric material that effectively prevents the diffusion of copper atoms, selecting silicon nitride as an interlayer dielectric material is less then desirable, since silicon nitride exhibits a moderately high permittivity, thereby increasing the parasitic capacitances of neighboring copper lines, which may result in non-tolerable signal propagation delays. Hence, a thin conductive barrier layer that also imparts the required mechanical stability to the copper is formed to separate the bulk copper from the surrounding dielectric material and only a thin silicon nitride or silicon carbide or silicon carbon nitride layer in the form of a capping layer is frequently used in copper-based metallization layers. Currently, tantalum, titanium, tungsten and their compounds with nitrogen and silicon and the like are preferred candidates for a conductive barrier layer, wherein the barrier layer may comprise two or more sub-layers of different composition to meet the requirements in terms of diffusion suppressing and adhesion properties.
Another characteristic of copper significantly distinguishing it from aluminum is the fact that copper may not be readily deposited in larger amounts by chemical and physical vapor deposition techniques, in addition to the fact that copper may not be efficiently patterned by anisotropic dry etch processes, thereby requiring a process strategy that is commonly referred to as the damascene or inlaid technique. In the damascene process, a dielectric layer is formed which is then patterned to include trenches and vias which are subsequently filled with copper, wherein, as previously noted, prior to filling in the copper, a conductive barrier layer is formed on sidewalls of the trenches and vias. The deposition of the bulk copper material into the trenches and vias is usually accomplished by wet chemical deposition processes, such as electroplating and electroless plating, thereby requiring the reliable filling of vias with an aspect ratio of 5 and more with a diameter of 0.3 μm or even less, in combination with trenches having a width ranging from 0.1 μm to several μm.
Electrochemical deposition processes for copper are well established in the field of electronic circuit board fabrication. However, the void-free filling of high aspect ratio vias is an extremely complex and challenging task, wherein the characteristics of the finally obtained copper-based interconnect structure significantly depend on process parameters, materials and geometry of the structure of interest. Since the geometry of interconnect structures is determined by the design requirements and may, therefore, not be significantly altered for a given microstructure, it is of great importance to estimate and control the impact of materials, such as conductive and non-conductive barrier layers, of the copper microstructure and their mutual interaction on the characteristics of the interconnect structure to insure both high yield and the required product reliability. In particular, it is important to identify, monitor and reduce degradation and failure mechanisms in interconnect structures for various configurations to maintain device reliability for every new device generation or technology node.
Accordingly, a great deal of effort has been invested in investigating the degradation of copper interconnects, especially in view of electromigration, in order to find new materials and process strategies for forming metal lines and vias. Although the exact mechanism of electromigration in copper lines is still not quite fully understood, it turns out that voids positioned in and on sidewalls and especially at interfaces to neighboring materials may have a significant impact on the finally achieved performance and reliability of the interconnects.
One failure mechanism, which is believed to significantly contribute to a premature device failure, is the electromigration-induced material transport, particularly along an interface formed between the copper and a dielectric capping layer acting as an etch stop layer during the formation of vias in the interlayer dielectric. Frequently used materials are, for example, silicon nitride and silicon carbon nitride, which exhibit a moderately high etch selectivity to typically employed interlayer dielectrics, such as silicon dioxide and a plurality of low-k dielectric materials, and also suppress the diffusion of copper onto the interlayer dielectric. Recent research results seem to indicate, however, that the interface formed between the copper and the etch stop layer is a major diffusion path for material transport during operation of the metal interconnect.
For state-of-the-art copper interconnect structures, the number and the strength of the bondings between the copper and the material of the etch stop layer is less compared to the strength and number of bondings formed between the copper and the conductive barrier layer, which covers the sidewalls and the bottom face of the metal interconnect. Consequently, the activation energy required for causing a stress-induced material transport, for instance in the form of electromigration, seems to be lowest at the interface between the etch stop layer and the copper for state-of-the-art copper interconnect structures, thereby rendering this interface the main cause for premature interconnect failure and reduced reliability. Therefore, great efforts have been made in developing new techniques that enable strengthening of this interface to increase the resistance against electromigration. For instance, in WO 02/050882, a method is described to form a copper alloy by depositing a dopant layer above a copper line and driving the dopants into the line. In alternative methods, a dopant is introduced into the copper line by ion implantation or the dopant material is introduced into the copper seed layer and is driven into the copper after the deposition of the bulk copper. While the first two techniques enable the formation of a copper alloy in the vicinity of the interface to the etch stop layer, which may reduce electromigration effects, the latter alternative may produce a significant amount of copper alloy throughout the entire copper line. However, while the former alternatives require additional process steps, thereby rendering the proposed technique cost intensive and possibly less reliable, the latter alternative may contribute to an increased electrical resistance of the copper line due to the presence of a moderate amount of copper alloy, which has a significantly higher electrical resistivity compared to pure copper.
In view of the above-described problems, there exists a need for a technique that allows the reduction of electromigration in copper interconnect structures without unduly increasing production costs and affecting the electrical conductivity of the metal interconnect.